The present invention relates to a semiconductor package, and more specifically, to a wafer level packaging technology and the method of forming the wafer level package.
In recent years, since the circuit devices in a chip are manufactured with a high density and it has been a trend to make semiconductor devices having small size. IC (integrated circuits) designers are tempted to scale down the size of each device and increase chip integration in per unit area. Typically, the semiconductor devices require protection from moisture and mechanical damage. The structure involves the technology of package. In the technology, the semiconductor dies or chips are usually individually packaged in a plastic or ceramic package. The package is required to protect the die and spread the heat generated by the devices. Therefore, the heat dissipation is very important in the semiconductor devices, particularly the power and the performance of the device increase. The conventional package is also used for performing full functionality testing of the chip. It is important that each device is kept as small as possible. Recently, there has existed a high interest of developing a package with a larger number of input and output. One of the solutions is to develop devices with ball grid array (BGA) and assembly technology. It is because that the renewed desire in high density hybrid is driven by the requirement of larger numbers of electrical connections, the increasing clock rate of digital systems.
Various types of package have been developed, recently. No matter what type of the package is, most of the packages are divided into individual chips before they are packaged. However, the wafer level packaging is a trend for the semiconductor package. One of the prior arts is shown below. Turning to FIG. 1, a plurality of dies 4 are formed on a surface of a semiconductor wafer 2. A glass 8 is attached on the surface of the wafer 2 having dies formed thereon by using an adhesive material 6. Then, the other surface of the wafer 2 without the dies is ground to reduce the thickness of the wafer 2, which is called back grinding, as shown in FIG. 2. Next, the wafer is then etched to isolate the ICs and a portion of the adhesive material 6 is exposed. This can be found in FIG. 3 and please turn to FIG. 4, a further glass 12 is attached on the surface that is opposite to the surface having dies 4 by another adhesive material 10. The next step is shown in FIG. 5, compliant layers 14 is formed on the top of the first glass followed by etching a portion of the first glass 8 and into the adhesive material 6 and 10, as shown in FIG. 6. This step is called notch process, thereby forming a trench 16 in the glass 8 and the adhesive material 6, 10. Over the compliant layer 14, solder balls will be formed thereon during the subsequent steps.
A layer 18 formed of lead is patterned on the surface of the first glass 8 and along the surface of the trench 14 for providing electrical connection. The layer 18 also covers the compliant layers 14, as shown in FIG. 7. Referring to FIG. 8, a solder mask 20 is successively formed over the surface of the lead layer 18 and the glass 8 to expose the surface aligned to the compliant layer 14. Therefore, the solder mask 20 exposes the lead over the compliant layer 14. Turning to FIG. 9 and FIG. 10, solder balls 22 are then implanted on the surface of the exposed lead 18, which is exposed by the solder mask 20 by a conventional process of implanting balls. The final step is to perform the dice process to etch the adhesive material 10 through the second glass 12 via the trench 16 resulting in the dies being separated. As known in the art, a dicing tape 24 is attached on the second glass before the step is used.
However, the process is too complicated. It needs the notch process and the step of etching the second glass 12 to separate the dies. Further, it includes the formation of the trench having a sharp profile. The lead formed thereon is not readily attached on the surface that will lead to open circuits. Hence the performance of the device is degraded.
An object of the present invention is to provide a package which has the real chip size package.
A further object of the present invention is to provide a package with a lower cost of manufacture and the purpose of the present invention is to disclose the wafer level package and the process of the same.
A yet object of the present invention is to make the package that is adapted to the wafer level burn-in test and the final test.
The present invention includes polishing the wafer backside by a grinder or the like. Subsequently, a material such as glass is laminated on the wafer backside surface of the wafer by using epoxy. The glass can be attached by using laminate process. Quartz or ceramic can replace the glass. Then, the wafer (or silicon) is etched to isolate the dies. An adhesive material with 1-2 mil is then coated on the second side of the wafer by means of vacuum coating process using epoxy. Then, a curing step is performed by using the ultraviolet (UV) radiation to harden the epoxy. A lapping (grinding) process is optional used to grind the epoxy on the wafer circuit side.
A plurality of openings are formed in the adhesive material and aligned to the pads of the dies (chips). Subsequently, a pad circuit re-distribution is arranged over the upper surface of the epoxy. The pad circuit can be composed of any conductive layer such as metal, alloy or the like. Preferably, the pad circuit is formed of Crxe2x80x94Cu alloy. A solder mask covers the epoxy and the pad circuit for isolation. A printing process is carried out to print solder on the pre-determined area and the solder contacts to the pad circuit. Then, the solder is re-flow at a temperature as known in the art. Then, the wafer is set to a testing apparatus for wafer level testing. A sawing process is next performed after the wafer-level test to separate the dies by cutting the scribe line, thereby obtaining the chip scale package (CSP).
A wafer level package of the present invention comprising a wafer having a plurality of dies formed thereon, wherein the wafer has a trench formed therein and over a scribe line. A glass is attached on the backside surface of the wafer by a first epoxy. A second epoxy is formed over the plurality of dies and refilled into the trench, wherein the plurality of dies has a plurality of pads formed thereon, A circuit layout is re-distribution on the second epoxy and connected to the plurality of pads. A solder mask is formed on the circuit layout and the second epoxy to expose a portion of the circuit layout. A solder ball is formed on the exposed portion and connected to the circuit layout.